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1 features ? pci_mt function implementing a 32-bit component interconnect (pci) interface optimized for at40k/at40kal/at94k architecture extensive simulation testing, includes test vectors uses 585 core cells fully-compliant design including: ? 32-bit, 33 mhz operation ? simplified local side (dma control engine) interface pci master features: ? memory read/write, one-cycle and burst ? i/o read/write, one-cycle and burst ? fully integrated dma engine including address counter register, byte counter register, control and status register, interrupt status register ? zero wait state pci read/write pci target features: ? type zero configuration space ? parity error detection ? memory read/write (1m byte) and i/o read/write (512k byte), one-cycle and burst ? configuration registers: device id, vendor id, status, command, class code, revision id, header type, latency timer, one memory base address, one i/o base address, subsystem id, subsystem vendor id, maximum latency, minimum grant, interrupt pin, and interrupt line description the pci_mt function provides a solution for integrating 32-bit pci peripheral devices, and is fully tested to meet the requirements of the pci specification. it is optimized for the at40k fpga architecture, enabling the designers to focus efforts on the custom logic surrounding the pci interface. the pci_mt macro is intended for use in atmel?s at40k/at40kal/at94k devices with remaining logic resources available for user- defined local side (dma control engine) customization. compliance summary the pci_mt function is compliant with the requirements specified in the pci special interest group?s (sig) pci local bus specification, rev.2.1. pci bus signals the following pci bus signals are used by the pci_mt function: input ? standard input-only signal output ? standard output-only signal bidirectional ? tri-state input/output signal sustained tri-state ? signal that is driven by one agent at a time. an agent that drives a sustained tri-state pin low must actively drive it high for one clock cycle before tri-stating it. another agent cannot drive a sustained tri-state signal any sooner than one clock cycle after it is released by the previous agent. open-drain ? signal that is wire-or with other agents. the signaling agent asserts the open-drain signal, and a weak pull-up resistor deasserts the open-drain signal. the pull-up resistor may take two or three pci bus clock cycles to restore the open- drain signal to its inactive state. pci master/target core function with dma AT40K-PCI ip core rev. 1083b?06/01 enter description to appear in data book toc and tag ?data book entry?
at40k pci 2 table 1 summarizes the pci bus signals interfacing the pci_mt to the pci bus. table 1. pci signals interfacing the pci_mt to the pci bus type name polarity description in clk ? clock, provides the reference signal for all other pci interface signals, except reset and intan. in reset low reset, initializes the at40k/20 interface circuitry, and can be asserted asynchronously to the pci bus clock edge. when active, the pci output signals are tri-stated and the open-drain signals, such as serrn , high impedance. in gntn low grant, indicates to the master device that it has control of the pci bus. every master device has a pair of arbitration lines ( gntn and reqn ) that connect directly to the arbiter. out reqn low request, indicates to the arbiter that the master wants to gain control of the pci bus to perform a transaction. tri-state ad[31:0] ? a time-multiplexed address/data bus; each bus transaction consists of an address phase followed by one or more data phases. the data phases occur when irdyn and trdyn are both asserted. tri-state cben[3:0] low a time-multiplexed command/byte enable bus. during the address phase it indicates command; during the data phase it indicates byte enables. tri-state par ? parity, shows even parity. the number of 1s on ad[31:0] , cben[3:0] , and par is an even number. sustained tri-state master: out target: in framen low frame, as output, indicates the beginning and duration for the current bus operation. when framen is initially asserted, the address and command signals are present on the ad[31:0] and cben[3:0] buses. it remains asserted during the data operation and is deasserted to identify the end of a transaction. sustained tri-state master: out target: in irdyn low initiator ready, is an output for the bus master to its target and indicates that the bus master can complete a data transaction. in a write transaction, it indicates that the valid data is on the ad[31:0] bus. in a read transaction, it indicates that the master is ready to accept the data on the ad[31:0] bus. sustained tri-state master: in target: out devseln low device select. target asserts devseln to indicate that it has decoded its own address. sustained tri-state master: in target: out trdyn low target ready. as target output, indicates that the target can complete the current data transaction. in a read operation, it indicates that the target is providing data on the ad[31:0] bus. in a write operation, it indicates that the target is ready to accept data on the ad[31:0] bus. sustained tri-state master: in target: out stopn low stop. it signals a target device request that indicates to the bus master to stop the current transaction. in idsel high initialization device select, is a chip select for configuration read or write operations. sustained tri-state perrn low parity error, indicates a data parity error. open-drain serrn low system error, indicates system error and address parity error. open-drain intan low interrupt a, an interrupt to the host, and must be used for any single-function device requiring an interrupt capability.
at40k pci 3 table 2 summarizes the pci bus signals interfacing the pci_mt to the local side peripheral device. parameters the pci_mt parameters set read-only pci bus configuration registers in the pci_mt; these registers are called device identification registers. see ?configuration registers? on page 7 for more information on device id registers. table 3 describes the parameters of the pci_mt function. table 2. pci signals interfacing the pci_mt to the local side type name polarity description in irqn low local side interrupt request. the local side peripheral device asserts it to signal a pci bus interrupt. for example, when the local side peripheral device requires a dma transfer, it could use the irqn input to request servicing from the host. in holdn low local hold, when asserted, it suspends the current dma transfer. as long as holdn is active, data transfers cannot occur between the pci_mt and the local side peripheral device. in req high local dma request. the local side peripheral device asserts req , which signals the pci_mt to request permission for a pci dma operation. dma write: in dma read: out ldat[31:0] ? a local data bus input, driven active by the local side peripheral device during pci_mt initiated dma write transactions (i.e., local side dma read transactions) and pci bus target read transactions. a local data bus output, driven by the pci_mt during pci_mt initiated dma read transactions (i.e., local side dma write transactions) and pci target write transactions. out pciholdn low local target chip select. when active, it notifies the peripheral device of an impending target transaction. any pci master device can read or write to a local side peripheral device through the pci_mt. the ackn and the pciholdn are never asserted at the same time. out rdn low read. the pci_mt asserts rdn to signal a read access to the local side peripheral device. the pci_mt uses rdn for reading from peripheral device target memory. for dma read operations, the pci_mt asserts the ackn and rdn signals. out wrn low write. the pci_mt asserts wrn to signal a write access to the local side peripheral device. the pci_mt uses wrn for writing to peripheral device target memory. for dma write operations, the pci_mt asserts the ackn and wrn signals. out ackn low local dma acknowledge. when low, it notifies the local side peripheral device that it has been granted a dma read or write transaction. the peripheral device can then transfer data to or from the pci bus through the pci_mt. out lreset low local reset. the pci_mt asserts it to reset the local side peripheral device. it follows the state of the lrst bit (bit 0 of the dma control status register). table 3. parameters name range default value (hexadecimal) description class_code 24-bit ff0000 class code register device_id 16-bit 0001 device id register device_vend_id 16-bit b325 device vendor id register revision_id 8-bit 01 revision id register subsystem_id 16-bit 0000 subsystem id register subsystem_vend_id 16-bit 0000 subsystem vendor id register
at40k pci 4 functional description the pci_mt macro consists of three main components: a defined 64-byte pci bus configuration register space and master control logic. pci bus target interface control logic, including target decode and local memory read/write signals. embedded dma control engine, and local side interface dma control logic, including read/write control and pci bus arbitration for master/target accesses. sustained tri-state signal operation the pci specification defines signals that are constantly sampled by different bus agents yet driven by one agent at a time, as sustained tri-state signals. for example, framen is constantly sampled by different pci bus targets (to detect the start of a transaction), and yet driven by one pci bus master at a time. for sustained tri-state signals, the pci specification requires using one clock cycle to drive the signals inactive before being tri-stated. the pci specification also requires that any sustained tri-state signal being released, such as the master device releasing ad[31:0] after asserting the address on a read operation, be given a full clock cycle to tri-state before another device can drive it. the pci specification defines a turn-around cycle as the clock cycle where a sustained tri-state signal is being tri- stated so that another bus agent can drive it. turn-around cycles prevent contention on the bus. master device signals and signal assertion figure 1. pci_mt master device signals figure 1 illustrates the pci-compliant master device signals interfacing the pci_mt with the pci bus. the signals are grouped by functionality, and signal directions are illus- trated from the perspective of the pci_mt operating as a master on the pci bus. a pci_mt master sequence begins with the assertion of reqn to request the pci bus. after receiving gntn from the arbiter (usually the pci host bridge) and after the bus idle state is detected, the pci_mt initiates the address phase by asserting framen and driving both the pci address on ad[31:0] and the bus command on cben[3:0] for one clock cycle. when the pci_mt is ready to present data on the bus, it asserts irdyn . at this point, the pci_mt master logic moni- tors the control signals driven by the target device. (a target device is determined by the decoding of the address and command signals present on the pci bus during the address phase of the transaction). the target device drives the control signals devseln , trdyn , and stopn to indicate one of the following: the data transaction has been decoded and accepted. the target device is ready for the data operation. (when both trdyn and irdyn are active, a data word is clocked from the sending to the receiving device.) the master device should stop the current transaction. clk reset idsel framen irdyn trdyn stopn devseln gntn reqn pa r ad[31:0] cben[3:0] perrn serrn intan pci-compliant master device error reporting signals interrupt request signal system signals interface control signals arbitration signals address, data & command signals pci_mt
at40k pci 5 target device signals and signal assertion figure 2. pci_mt target device signals figure 2 illustrates the pci-compliant target device signals interfacing the pci_mt with the pci bus. the signals are grouped by functionality, and signal directions are illus- trated from the perspective of the pci_mt operating as a target on the pci bus. a pci_mt target sequence begins when the master device asserts framen and drives the address of the target and the command on the pci bus. when the target device decodes its address on the pci bus, it asserts devseln to indicate to the master that it has accepted the transaction. the master will then assert irdyn to indicate to the target device that: for a read operation, the master device can complete a data transaction. for a write operation, valid data is on the ad[31:0] bus. when the pci_mt functions as the selected target device, it will drive the control signals devseln , trdyn , and stopn as discussed in ? master signals & signal assertion ? . as a target device, pci_mt supports both single-cycle and burst-cycle accesses; it drives trdyn active in both cases, stopn is driven active only in the case of a single-cycle access. when qualified by an active irdyn signal, a data word is clocked from the sending to the receiving device. parity signal operation all bus cycles include parity. every device that transmits on the ad[31:0] bus must also drive the par signal, including master devices outputting the address. because parity on the pci bus is even, the number of logic 1s on ad[31:0] , cben[3:0] , and par must be even. parity checking is not required, but can be enabled through the agent ? s pci com- mand register. system, address and data parity errors are presented on the serrn output, address and data parity errors are presented on the perrn output. the par bit lags the ad[31:0] bus by one clock cycle, and parity error signal lag the par bit by one clock cycle; thus, parity error signals lag the address or data by two clock cycles. clk reset idsel framen irdyn trdyn stopn devseln pa r ad[31:0] cben[3:0] perrn serrn intan pci-compliant target device error reporting signals interrupt request signal system signals interface control signals address, data & command signals pci_mt
at40k pci 6 bus master commands when the pci_mt acquires mastership of the pci bus, it can initiate a memory read or memory write command. during the address phase of a transaction, the cben[3:0] bus is used to indicate the transaction type. the pci_mt supports io read/write, memory read/write, and configuration read/write commands. when operating as a master device, the pci_mt executes standard io or memory read/write operations. when operating as a target, the pci_mt responds to standard io or memory read/write transactions. the pci_mt also responds to configuration read/write operations. table 4 summarizes the pci bus commands that are sup- ported by the pci_mt. table 4. pci bus command support summary cben[3:0] value bus command cycle target support master support 0010 io read yes yes 0011 io write yes yes 1010 memory read yes yes 1011 memory write yes yes 1010 configuration read yes no 1011 configuration write yes no others ? no no
at40k pci 7 configuration registers each logical pci bus device includes a block of 64 configuration dwords reserved for the implementation of its configuration registers. the format of the first 16 dwords is defined by the pci sig?s pci local bus specification compliance checklist, revision 2.1 , which defines two header formats, type one and type zero. header type one is used for pci-to-pci bridges; header type zero is used for all other devices, including the pci_mt. table 5 displays the defined 64-byte configuration space. the registers within this range are used to identify the device, control the pci bus functions, and provide pci bus status. the areas in italics indicate registers that are sup- ported by the pci_mt. table 6 summarizes the pci_mt-supported configuration registers address map. read/write refers to the status at run time, i.e., from the perspective of other pci bus agents. the specified default state is defined as the state of the register when the pci bus is reset. table 5. pci bus configuration registers address byte 3 byte 2 byte 1 byte 0 00h device id vendor id 04h status register command register 08h class code revision id 0ch bist header type latency timer cache line size 10h base address register 0 (memory) 14h base address register 1 (io) 18h base address register 2 1ch base address register 3 20h base address register 4 24h base address register 5 28h card bus cis pointer 2ch subsystem id subsystem vendor id 30h expansion rom base address register 34h reserved 38h reserved 3ch maximum latency minimum grant interrupt pin interrupt line
at40k pci 8 vendor id register (offset = 00 hex) vendor id is a 16-bit read-only register that identifies the manufacturer of the device (e.g., atmel for the pci_mt). the value of this register is assigned by the pci sig; the default value of this register is the atmel vendor id value, which is b325 hex. however, by setting the device_vend_id parameter (see table 3), designers can change the value of the vendor id register to their pci sig-assigned vendor id value. (see table 7.) device id register (offset = 02 hex) device id is a 16-bit read-only register that identifies the type of device. the value of this register is assigned by the manufacturer (e.g., atmel assigned the value of the device id register for the pci_mt). the default value of this register is 0001 hex; however, by setting the device_id parameter (see table 3), designers can change the value of the device id register. table 6. pci_mt-supported configuration registers address map address offset range reserved bytes used/ reserved read/write mnemonic register name 00 00 ? 01 2/2 read ven_id vendor id 02 02 ? 03 2/2 read dev_id device id 04 04 ? 05 2/2 read/write comd command 06 06 ? 07 2/2 read/write status status 08 08 ? 08 1/1 read rev_id revision id 09 09 ? 0b 3/3 read class class code 0d 0d ? 0d 1/1 read/write lat_tmr latency timer 0e 0e ? 0e 1/1 read header header type 10 10 ? 13 4/4 read/write bar0 base address register 0 14 14 ? 17 4/4 read/write bar1 base address register 1 2c 2c ? 2d 2/2 read sub_ven_id subsystem vendor id 2e 2e ? 2f 2/2 read sub_id subsystem id 3c 3c ? 3c 1/1 read/write int_ln interrupt line 3d 3d ? 3d 1/1 read int_pin interrupt pin 3e 3e ? 3e 1/1 read min_gnt minimum grant 3f 3f ? 3f 1/1 read max_lat maximum latency table 7. vendor id register format data bit mnemonic read/write definition [15:0] ven_id read pci vendor id
at40k pci 9 command register (offset = 04 hex) command is a 16-bit read and write register that provides basic control over the ability of the pci_mt to respond to and/or perform pci bus accesses. (see table 8.) table 8. command register format data bit mnemonic read/write definition 0unused ?? 1 mem_ena read/write memory access enable. when high, it enables the pci_mt to respond to the pci bus memory accesses as a target. because the dma registers are set via memory target accesses, the mem_ena bit must be set as part of the initialization operation for the pci_mt to perform dma transfers. 2 mstr_ena read/write master enable. when high, it enables the pci_mt to acquire mastership of the pci bus. for the pci_mt to perform dma transfers, the mstr_ena bit must be set as part of the initialization operation. [5:3] unused ?? 6 perr_ena read/write parity error enable. when high, it enables the pci_mt to report parity errors via the perrn output. 7unused ?? 8 serr_ena read/write system error enable. when high, it enables the pci_mt to report system errors via the serrn output. [15:9] unused ??
at40k pci 10 status register (offset = 06 hex) status is a 16-bit read and write register that provides the status of bus-related events. read transactions to the sta- tus register behave normally. however, write transactions are different from typical write transactions in that bits in the status register can be cleared but not set. a bit in the sta- tus register is cleared by writing a logic one to that bit. for example, writing the value of 4000 hex to the status regis- ter clears bit number 14 and leaves the rest of the bits unchanged. the default value of the status register is 0000 hex. (see table 9.) revision id register (offset = 08 hex) revision id is an 8-bit read-only register that identifies the revision number of the device. the value of this register is assigned by the manufacturer (e.g., atmel for the pci_mt). therefore, the default value of this register is set as the revision number of the pci_mt, (see table 10). however, designers can change the value of the revision id register by setting the revision_id parameter (see table 3). class code register (offset = 09 hex) class code is a 24-bit read-only register divided into three sub-registers: base class, sub-class, and programming interface. refer to the pci local bus specification, rev.2.1 for detailed bit information. (see table 11.) the default value of this register is ff0000 hex; however, designers can change the value by setting the class_code param- eter (see table 3). table 9. status register format data bit mnemonic read/write definition [7:0] unused ?? 8 dat_par_rep read/write data parity error reported. when high, it indicates that during a read transaction the pci_mt asserted the perrn output as a master device, or that during a write transaction the perrn was asserted by a target device. this bit is high only when the perr_ena bit (bit 6 of the command register) is also high. [10:9] devsel_tim read/write device select timing. it indicates target access timing of the pci_mt via the devseln output. the pci_mt is designed to be a slow target device. 11 unused ?? 12 tar_abrt read/write target abort. when high, it indicates that the current target device transaction has been terminated. 13 mstr_abrt read/write master abort. when high, it indicates that the pci_mt drove the serrn output active, i.e., a system error has occurred. 14 serr_set read/write system error enable. when high, it enables the pci_mt to report system errors via the serrn output. 15 det_par_err read/write detected parity error. when high, it indicates that the pci_mt detected either an address or data parity error. even if parity error reporting is disabled (via perr_ena ), the pci_mt will set this bit. table 10. revision id register format data bit mnemonic read/write definition [7:0] rev_id read pci revision id table 11. class code register format data bit mnemonic read/write definition [23:0] class read class code
at40k pci 11 latency timer register (offset = 0d hex) the latency timer register is an 8-bit register with bits 2, 1, and 0 tied to gnd. the register defines the maximum amount of time, in pci bus clock cycles, that the pci_mt can retain ownership of the pci bus. after initiating a transac- tion, the pci_mt decrements its latency timer by one on the rising edge of each clock. the default value of the latency timer register is 00 hex. (see table 12.) header type register (offset = 0e hex) header type is an 8-bit read-only register that identifies the pci_mt as a single-function device. the default value of this register is 00 hex. (see table 13.) base address register zero (offset = 10 hex) base address register zero (bar0) consists of a 12-bit register (bits 31 through 20) that determines the base memory address of the pci_mt target space. its default value is 000 hex. (see table 14.) table 12. latency timer register format data bit mnemonic read/write definition [2:0] lat_tmr read latency timer register [7:3] lat_tmr read/write latency timer register table 13. header type register format data bit mnemonic read/write definition [7:0] header read pci header type table 14. base address register zero format data bit mnemonic read/write definition 0 mem_ind read memory indicator. hardwired to a zero, it indicates a memory address decoder. [2:1] mem_type read memory type. it indicates the type of memory that can be implemented in the pci_mt memory address space. these bits are tied to gnd, which indicates that the memory block can be located anywhere in the 32-bit address space. 3 pre_fetch read memory prefetchable. it indicates whether the block of memory defined by bar 0 is prefetchable by the host bridge. in the pci_mt, the address space is not prefetchable, i.e., it reads as low. [19:4] unused ?? [31:20] bar0 read/write base address register zero.
at40k pci 12 base address register one (offset = 14 hex) base address register one (bar1) consists of a 12-bit register (bits 31 through 20) that determines the base i/o address of the pci_mt target space. its default value is 000 hex (see table 15). subsystem vendor id register (offset = 2c hex) subsystem vendor id register is a 16-bit read-only regis- ter that identifies add-in cards designed by different vendors but with the same functional device on the card. the value of this register is assigned by pci sig (see table 16). its default value is 0000 hex; however, design- ers can change the value by setting the subsystem_vend_id parameter, (see table 3). subsystem id register (offset = 2e hex) subsystem id register is a 16-bit read-only register that identifies the subsystem; the value of this register is defined by the subsystem vendor, i.e., the designer (see table 17). its default value is 0000 hex; however, design- ers can change the value by setting the subsystem _id parameter (see table 3). interrupt line register (offset = 3c hex) the interrupt line register is an 8-bit read/write register that defines to which system interrupt request line (on the system interrupt controller) the intan output is routed. the interrupt line register is written to by the system software on power-up; the default value is ff hex (see table 18). interrupt pin register (offset = 3d hex) the interrupt pin register is an 8-bit read-only register that defines the pci_mt pci bus interrupt request line to be intan . its default value is 01 hex (see table 19). minimum grant register (offset = 3e hex) minimum grant register is an 8-bit read-only register that defines the length of time the pci_mt would like to retain the mastership of the pci bus. the value set in this register indicates the required burst period length in 250-ns incre- ments. the pci_mt request a timeslice of 4 microseconds. its default state is 10 hex (see table 20). table 15. base address register one format data bit mnemonic read/write definition 0 io_ind read i/o space indicator. it indicates whether the register is i/o or a memory address decoder. in the pci_mt, the io_ind bit is tied to 1, which indicates an i/o address decoder. 1 io_res read reserved, returns zero. [19:2] unused ?? [31:20] bar1 read/write base address register one. table 16. subsystem vendor id register format data bit mnemonic read/write definition [15:0] sub_vend_id read pci subsystem/ vendor id table 17. subsystem id register format data bit mnemonic read/write definition [15:0] sub_id read pci subsystem id table 18. interrupt line register format data bit mnemonic read/write definition [7:0] int_ln read/write interrupt line register table 19. interrupt pin register format data bit mnemonic read/write definition [7:0] int_pin read interrupt pin register table 20. minimum grant register format data bit mnemonic read/write definition [7:0] min_gnt read minimum grant register
at40k pci 13 maximum latency register (offset = 3f hex) maximum latency register is an 8-bit read-only register that defines the frequency in which the pci_mt would like to gain access to the pci bus. the value set in this register is 00 hex, which indicates that the pci_mt has no major requirements for maximum latency (see table 21). pci bus transactions this section describes pci_mt pci bus transactions. the pci_mt accesses the pci bus for three types of transactions: device configuration target master the at40k_pci core kit comes with 3 simulation files. the following descriptions are extracts from the full waveform files supplied with the core. pci_mt.cmd: the command file, defines the setting (signals, timing,..) for the pre-layout simulation of the core. pci_mt.sen: contains the test vectors, required by the pci_mt.cmd at run-time. each group of vectors from pci_mt.sen is associated with a command line in the pci_mt.cmd file. for an easy follow-through, each group has its own id, at the beginning (i.e., |00_hardware reset, |00a_***,..). this way a test vector group from the pci_mt.sen file can be easily paired-up with its associated command line from the pci_mt.cmd file. we will identify these groups as group_00, group_00a, etc. pci_mt.wfm: the waveform file, generated as a result of the pre-layout simulation run (running the pci_mt.cmd and pci_mt.sen under viewsym ). configuration transactions a configuration transaction is generated by either a host-to- pci bridge or pci-to-pci bridge access. in the address phase of a configuration transaction, the pci bridge will drive the idsel signal on the pci bus agent that it wants to access. if a pci bus agent decodes the configuration com- mand and detects its idsel to be high, the agent will claim the configuration access and assert devsel . group_00a (configuration read, device id & ven- dor id registers) shows the timing of a pci_mt configuration read transaction. during the address phase, the address of the device id & vendor id registers is present on the adins[31:0] bus, while the cbeins[3:0] bus provides the configuration read command code (i.e., a hex). immediately after the address phase, the next clock cycle the master deasserts framen and asserts irdyn , indi- cating both of the following: the transaction contains a single data phase. the master device is ready to read the data that the pci_mt has presented on the ad[31:0] bus. at the same time the master device tri-states the ad[31:0] bus (the case of a turn-around cycle). the next clock cycle pci_mt can drive the ad[31:0] bus, by asserting the aden[3:0] lines (their state goes from 0000 to 1111, or f hex). it also asserts devselout , which indicates to the master device that the pci_mt has accepted the transaction; at the same time, the target starts driving the devseln , trdyn , and stopn signals on the pci bus, by asserting the oe_tar signal. the devselout is then sam- pled by the master device (as devseln ) on each rising-edge of the clock. two clock cycles later (the pci_mt is a slow decode device during target and configuration read/write transactions) pci_mt asserts trdyout . at the same time the irdyin signal is still asserted by the master, therefore a data transfer takes place. thus, the data present on the inner ados[31:0] bus is transferred to the ad[31:0] bus as the value of the device id & vendor id registers. because the pci_mt does not support configuration read/write burst accesses, it will assert stopout to indicate a disconnect to the master. the master will sample the stopn signal and will subsequently end the transaction by deasserting irdyin . after the last data transfer cycle of the current transaction, the target device keeps the oe-tar asserted for one more cycle, at the same time driving devseln , trdyn , and stopn high. thus, the sustained tri-state signal requirement is met, i.e., driving the signal high one clock cycle before releasing it. group_01 (configuration write, status & com- mand registers, 5555h) shows the timing of a pci_mt configuration write transaction. the protocol is identical to the protocol discussed in the pci configuration read transaction except for the command code (which is b hex for configuration write) and the aden[3:0] bus, which is no longer asserted after the address phase. table 21. maximum latency register format data bit mnemonic read/write definition [7:0] max_lat read maximum latency register
at40k pci 14 configuration read, device id and c vendor id register (group_00a) configuration write, status and command registers (group_01) clk framen idsel cbens ads oe_tar 0z irdyn pciholdn trdyn devselout stopn a 001b325 00000000 zzzzzzzz zzzzzzzz clk framen idsel cbens ads oe_tar b z z 0 irdyn pciholdn trdyn devselout stopn 00000004 55555555 zzzzzzzz zzzzzzzz zzzzzzzz
at40k pci 15 target transactions a target read/write transaction begins after the master acquires mastership of the pci bus and asserts framen to assert the beginning of a new transaction. the pci_mt latches the address and command signals on the first clock edge when framen is asserted and starts the address decode phase. the pci_mt supports two types of target read/write transactions: internal target read : target read/write transaction from the internal dma registers. external target read : target read/write transaction from the local side target memory space. target read transactions the sequence of events in both target read transactions (internal & external) is identical; however, the timing is not. a target read transaction from the local side target memory space requires more time because the pci_mt must wait for the local side. group_0e (dma configuration read, terminal count & command register) shows the timing of a pci_mt inter- nal target (dma register) read transaction. the protocol is identical to the protocol discussed in the pci configuration read transaction except for the target registers, which are the dma terminal count register, the dma address reg- ister & the dma command register. group_1f (i/o read, 1 dword shows the timing of a pci_mt external target (dma register) read transaction. the protocol is identical to the protocol discussed in the pci configuration read transaction except for the target, which is the local side target memory page. group_1e, i/o write, 4 dwords, wait before the fourth dword, shows the timing for a target write transaction. dma configuration read, terminal count and command register (group_oe) clk idsel framen pciholdn trdyn cbens ads stopn irdyn 0 devseln zz 2 zzzzzzzz zzzzzzzz 55580001 0000d04d
at40k pci 16 i/o read, 1 dword (group_1f) clk framen stopn irdyn trdyn pciholdn devseln ldats ackn req wrn lden_ holdn rdn idsel cbens cbens ads z2 0 z 55500001 xxxxxxxx 77777777 11111111 zzzzzzzz zzzzzzzz 11111111 zzzzzzzz
at40k pci 17 i/o write, 4 dwords, wait before the fourth dword (group_1e) clk framen stopn irdyn trdyn pciholdn devseln ldats ackn wrn lden_ holdn rdn gntn cbens ads z 30 z 55500001 xxxxxxxx 77777777 88888888 zzzzzzzz zzzzzzzz 99999999 aaaaaaaa zzzzzzzz zzzzzzzz 77777777 88888888 99999999 aaaaaaaa
at40k pci 18 dma operation this section provides operating details of the dma engine, and it covers the following: target address space internal target register memory map dma registers dma transactions general programming guidelines target address space the pci_mt memory-mapped target registers (internal and external) are read and/or written over the pci bus in table 15 memory space. accesses to or from bar1 memory space occur in 32-bit transfers. table 22 list the pci_mt memory space address map. the pci_mt bar1 address space is 1m byte of contiguous address divided into two 512k byte spaces. the lower 512k byte region (internal target address space) contains the pci_mt dma control registers, and the upper region (external target address space) contains user-defined i/o space. internal target registers memory map internal pci_mt target address space is used for the dma registers, including the dma terminal_count, control & status register, dma command enables register, and the dma address counter register. table 23 lists the pci_mt dma registers memory map. table 22. memory space address map memory space block size (dwords) address offset words used/reserved read/write description bar1 128 00000h-7ffffh 3/128k read/write dma registers bar1 128 80000h-fffffh 128k/128k read/write user-defined i/o space (128k dwords) table 23. internal target registers memory map range reserved bytes used read/write mnemonic default state (hex) register name 00000h-00003h 00 ? 03 4/4 dma_tccs 00000000 dma terminal_count, control & status 00004h-00004h 00 ? 00 0/2 dma_cesr 00000000 dma command enables select 00008h-0000bh 00 ? 03 4/4 dma_acr 00000000 dma address counter
at40k pci 19 dma registers this section describes the dma registers. the specified default state is defined as the state of the storage element when the pci bus is reset. the pci_mt contains the follow- ing dma registers: terminal_count, control & status byte enables address counter terminal_count, control and status register (offset = 00000 hex) the dma terminal_count, control & status register (dma_tccs) configures the pci_mt dma engine, directs the pci_mt operation, and provides status of the current mem- ory transfer (see table 24). table 24. dma terminal_count, control and status register format data bit mnemonic read/write definition 0 lrst read/write local reset. this bit serves as a software reset to the local side add-on logic (see table 2). the lreset output of the pci_mt is active as long as the lrst bit is low. the lreset output is also active for pci bus resets. 1 flush read/write flush buffer. when high, flush marks all bytes in the internal 2 x 32-bit buffer as invalid and resets dmatc and adloaded (bits 10 and 11). the flush bit also resets itself; therefore, it always reads as zero. the flush bit should never be set while dmaon is set, because a dma transfer is in progress. 2 intena read/write pci interrupt enable. it enables the intan output when either the errpend or dmatc bits are driven high, or when req signal is active. 3 tcidis read/write transfer complete interrupt disable. when high, it disables dmatc (bit 10) from generating pci bus interrupts. 4 dmaen read/write dma enable. when high, it allows the pci_mt to respond to dma requests from the local side ( req ) as long as the pci bus activity is not stopped due to a pending interrupt, etc. 5 burst read/write burst enable. when high, the master transfers 4 dwords per transaction; if low, the master transfers 1 ? dword only. 6 intirq read when high, it indicates that the local side is requesting an interrupt, i.e., the req input is asserted. 7 errpend read when high, it indicates that an error occurred during a pci_mt-initiated pci bus transfer, and the interrupt handler must read the pci configuration status register and clear the appropriate bits. any one of the following three pci status register bits can assert errpend : mstr_abrt , tar_abrt , and det_par_err . see control & status register. 8 intpend read the pci_mt automatically asserts intpend to indicate that a pci_mt interrupt is pending. the three possible interrupt signals from the pci_mt are err_pend , dma_tc , and intirq . 9 dmaon read dma on. when high, it indicates that the pci_mt can request mastership of the pci bus ( reqn ) if prompted by the local side (i.e., an active req ). the dmaon bit is high when the address is loaded ( adloaded ), the dma is enabled, and there are no pending errors. the dma transfer sequence actually begins when the dmaon bit becomes set. under normal conditions (i.e., dma is enabled and no errors are pending) the dmaon bit becomes set when a write transaction to the dma address counter register occurs. 10 dmatc read when high, it indicates that the pci_mt-initiated dma transfer is complete. when the pci_mt sets the dma_tc bit, an interrupt will be generated on the intan output as long as interrupts are enabled by the intena bit (bit 2) and not disabled by the tcidis bit (bit 3). the dmatc bit is reset in one of three ways: a read transaction to the dma_tccs ; a write transaction to the dma_tccs , which sets the flush bit (bit 1); or by asserting the rstn input from the pci bus.
at40k pci 20 dma transactions the pci_mt dma engine, which consists of a 4 x 32-bit fifo and three programmable registers, is the control channel when the pci_mt acquires mastership of the pci bus. as a master device, the pci_mt performs dma read and write transactions to system memory, or to another pci bus agent capable of accepting burst target data transfers. a dma read transaction from memory to the local side con- sists of two separate transfers: one or more (4, if burst ) pci bus dword reads from the pci bus to the fifo. an equivalent number of dword transfers from the 32- bit register to the local side. all dma read transactions from the pci_mt use a memory read command. for example, see ? dma configuration read, terminal count and command register (group_oe) ? on page 15 and ? i/o read, 1 dword (group_1f) ? on page 16. similarly, a dma write transaction from the pci_mt to sys- tem memory consists of two separate transfers: dword transfers from the local side to the fifo. one or more (4, if burst) pci dword writes from the fifo to a pci agent. all dma (pci bus) write transactions from the pci_mt use the memory write command. group_26a1, master write, 4 dwords, wait before the second dword, shows the timing for a master write transaction. group_30a2, master read, 4 dwords, wait before the third dword, shows the timing for a master read transaction. 11 adloaded read when high, it indicates that the address has been loaded via the dma_acr . this bit is cleared in one of three ways: when the dma operation is complete and the dmatc bit is set; when the flush bit is set; or when the rstn input is asserted from the pci bus. the adloaded bit triggers the beginning of a dma operation and is automatically set by the pci_mt when a write operation to the dma_ccst is performed. therefore, the dma_acr should be written to last when a dma operation is being loaded into the dma registers. [13-12] unused ?? [31:14] tc read/write terminal counter register. table 24. dma terminal_count, control and status register format (continued) data bit mnemonic read/write definition
at40k pci 21 master write, 4 dwords, wait before the second dword (group_26a1) clk gntn stopn irdyin trdyn devseln ackn wrn lden_ framen holdn rdn reqn cbens ads z70 0 xxxxxxxx xxxxxxxx zzzzzzzz ldats fffc40b0 bbbbbbbb aaaaaaaa 99999999 88888888 zzzzzzzz bbbbbbbb aaaaaaaa zzzzzzzz zzzzzzzz 99999999 88888888
at40k pci 22 master read, 4 dwords, wait before the third dword (group_30a2) clk gntn stopn framen trdyn irdyn devseln ackn wrn lden_ holdn rdn reqn cbens ads z 60 z xxxxxxxx xxxxxxxx zzzzzzzz ldats fffc40b0 zzzzzzzz bbbbbbbb 99999999 77777777 66666666 zzzzzzzz 55555555 44444444 zzzzzzzz xxxxxxxx 77777777 66666666 55555555 44444444
at40k pci 23 implementation description figure 3. top level core interface adin[31:0] adout[31:0] aden[3:0] cbenin[3:0] cbenout[3:0] cbenen idsel framein frameout frameen irdyin irdyout de_irdy trdyin trdyout devselin devselout stopin stopout de_par perrin perrout perren serrn reqout gntin intan clk rst lden_ iq[31:0] ldin[31:0] pcihold_ lrd_ lwr_ lack_ lreset_ lhold_ lreq_ lirq_ pcimacro lden_ iq[31:0] ldin[31:0] oe $array = 32 ldat[31:0] pa d a q pciholdn rdn pa d pa d wrn pa d ackn pa d lreset pa d holdn pa d req pa d irqn pa d reset pa d rs q rst clock pa d c q iclk rsbuf pa d gntn intan pa d reon pa d pa d a q a inta serrn iserr ireq ignt pa d oe perrn perren perrin perrout pa d oe pa r de_par parin pa r o u t parin parout de_tar pa d oe stopn stopin stopout de_tar pa d oe devseln de_tar idevselin idevselout pa d trdyin trdyin trdyout q a pa d irdyin q a de_irdy irdyin irdyout pa d q a framein frameout frameen framen pa d q idsel idsel pa d q a cbenin[3:0] cbenout[3:0] cbenen cben[3:0] pa d q a adout[31:0] aden[3:0] aden0 adin[7:0] adout[7:0] ad[7:0] pa d q a aden1 adin[15:8] adout[15:8] ad[15:8] pa d q a aden2 adin[23:16] adout[23:16] ad[23:16] pa d q a aden3 adout[31:24] ad[31:24] oe $array=8 oe $array=8 oe $array=8 $array=8 oe $array=4 oe q a q a q a q a a gclkbuf gnd gnd a a a a a a a a adin[31:24] adin[31:24] oe oe pci_mt pci_bus_core master & target
at40k pci 24 figure 4. internal core block diagram arbiter0 bus arbiter pcireq dmahold pcihold_ loc_gnt pci_gnt r clk r clk master eadphase wrm adrphase rdt lcycle cmdoc[6:0] c[7:0] ca[3:0] cfgrd pcicmdo tabort lden_ aden[3:0] id[32:12] cmdsdec pci commands decoding r clk adout[31:20] idsel framein itrdydat r clk cmdt5 dmahold master target pcihold_ cmdm4 cmdm3 cmdm0 cmdt5 cmdt3 cmdid[11:0] ca[3:0] pcihold tcmdo dmahold mcmdo ldin[31:0] hostrqok adrphase ladrwr rdtc longhit lden_ lreset_ lreq_ lhold_ lirq_ lwr_ lrd_ lack_ frameset comp clrtrdy dmatc perrenab lden_ lreset_ lreq_ lhold_ lirq_ lwr_ lrd_ lack_ r clk itrdydat pendreq irdyout adout[31:0] adin[31:0] intan parout devselin trdyin irdyin framein id[31:0] iq[31:0] r clk pci address/ data buffering addrbufs cmdc3 cmdc6 cmdc5 cmdc1 cmdd[11:0] ldin[31:0] allerrs r clk iq[31:0] id[31:27] id24 id[15:11] id[8:0] framein r clk allerrs ca[2:0} c[7:0] si[31:26] conf[4:0] cfgrd to config configuration registers cmdt3 cmdt4 cmdt2 si26 si30 si31 conf3 conf4 si[31:26] conf[4:0] perrenab m_oe_ad mterm newframe sterm s_oe_ad so24 so30 s031 pyerresp serrenab r clk parout oe_par parin perrin perrout perren serrn r clk parity checking/ generation parity to pcicmdo dmahold master dmatc mterm frameset cmdom[4:0] recmasta rectarga r clk cbenen reqout gntin framein frameout frameen devselin de_irdy irdyin trdyin stopin r clk master master interface cmdm[4:0] si29 si28 master target clritrdy tabort cmdot[20:0] shorthit longhit allhits cmdrdwr cmdwr r clk framein irdyin trdyin trdyout devselout stopout de_tar target target interface cmdt[5:0] cmdc2 cmdc1 cmdc0 cmdc4 cmdc3 cbenen reqout gntin framein frameout frameen devselin de_irdy irdyin trdyin stopin trdyout devselout stopout de_tar aden[3:0] pendreq adin[3:0] adin[31:19] cbenin[3:0] cbenout[3:0] cmdod[11:0] cmdc[6:0] c[7:0] ca[3:0] cmdm2 cmdm1 ca[2:0] cmdm3 si27 adin[31:19] r clk oe_par parin perrin perrout perren serrn irdyout adout[31:0] adin[31:0] intan parout itrdydat cbenin[3:0] cbenout[3:0] idsel id[31:12] adin[3:0] iq[31:20] id[31:0] iq[31:0] id[31:27] id[15:11] id[8:0] id24 allerrs rst clk
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